This invention relates, in general, to thin film transistors and, more particularly, to dual gate thin film transistors manufactured with a power MOSFET process.
Typically, thin film transistors are fabricated from polysilicon which, because of the presence of grain boundaries, has a high density of trap states. A large number of trap states degrades several transistor characteristics including sub-threshold swing, threshold voltage, and drive current. In particular, the large number of trap states increases both the sub-threshold swing and the threshold voltage of the transistor, and reduces the transistor drive current.
To improve these transistor characteristics, dual gate thin film transistors have been developed. A reduction in both the sub-threshold swing and threshold voltage, as well as an increase in transistor drive current, results from incorporating an additional gate into thin film transistors. Typically, the additional gate is made from polysilicon.
One approach to manufacturing dual gate thin film transistors has been to use three layers of polysilicon wherein two of the three layers form gate regions. Unfortunately, this approach adds several processing steps to the power MOSFET process. Further, incorporating a dual gate thin film transistor having polysilicon as the additional gate into the power MOSFET process is expensive. Accordingly, it would be advantageous to have a method for manufacturing dual gate thin film transistors that is easily and inexpensively integrated into existing integrated circuit fabrication processes, especially power MOSFET processes.